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1 load current (a) 0.0001 70 efficiency (%) 80 90 100 0.001 1 10 0.01 0.1 3111 ta01b 60 50 40 30 v in = 2.7v v in = 5v v in = 12v burst pwm typical application features description 15v, 1.5a synchronous buck-boost dc/dc converter the lt c ? 3111 is a fixed frequency, synchronous buck- boost dc/dc converter with an extended input and output range. the unique 4- switch, single inductor architecture provides low noise and seamless operation from input voltages above, below or equal to the output voltage. with an input and output range of 2.5 v to 15v , the ltc3111 is well suited for a wide variety of single or multiple-cell batteries, back - up capacitor or wall adapter source applica - tions. low r ds(on) internal n-channel mosfet switches and selectable pwm or burst mode operation produce high efficiency over a wide range of operating conditions. an accurate run pin allows the user to program the turn-on threshold voltage of the converter. other features include: short-circuit protection, internal soft-start and thermal shutdown. the ltc3111 is offered in both thermally enhanced 14-lead (3mm 4 mm 0.75 mm) dfn and 16- lead msop packages. 5v, 800khz wide input voltage buck-boost regulator applications n regulated output with v in above, below or equal to v out n 2.5 v to 15v input and output voltage range n 1.5a continuous output current: v in 5v, v out = 5v, pwm mode n single inductor n accurate run threshold n up to 95% efficiency n 800khz switching frequency, synchronizable between 600khz and 1.5mhz n 49a no-load quiescent current in burst mode ? operation n output disconnect in shutdown n shutdown current < 1a n internal soft-start n small, thermally enhanced 14-lead (3mm 4mm 0.75mm) dfn and 16-lead msop packages n 3.3v or 5v from 1, 2 or 3 li-ion, multiple-cell alkaline/nimh batteries n rf transmitters n military, industrial power systems l, lt , lt c , lt m , linear technology, the linear logo, burst mode, ltspice are registered trademarks and no r sense and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6404251, 6166527, 5481178, 6304066, 6580258. sw1 0.1f 27pf 1f 33pf 1m 191k 3111 ta01a 20k 680pf 26.1k 0.1f v in 2.5v to 15v 4.7h sw2 bst1 bst2 v in ltc3111 pgnd sgnd v out 22f v out 5v 1.5a (v in > 5v) 10f pwm/sync burst pwm run fb v cc snsgnd comp off on efficiency at 5v out ltc 3111 3111fa for more information www.linear.com/ltc3111
2 pin configuration absolute maximum ratings v in voltage ................................................. C 0.3 v to 16 v v out voltage .............................................. C 0.3 v to 16 v sw1 voltage ( note 4) ................... C 0.3 v to (v in + 0.3 v) sw2 voltage ( note 4) ................. C 0.3 v to (v out + 0.3 v) bst 1 voltage ................... ( v sw 1 C 0.3 v) to (v sw 1 + 6v) bst 2 voltage ................... ( v sw 2 C 0.3 v) to (v sw 2 + 6v) run voltage ............................................... C0.3 v to 16 v pwm / sync , v cc voltage ............................. C 0.3 v to 6v fb , comp , voltage ....................................... C 0.3 v to 6v (notes 1, 3) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sgnd pwm/sync v cc nc v out sw2 bst2 comp fb snsgnd run v in sw1 bst1 top view 15 pgnd de package 14-lead (4mm 3mm) plastic dfn t jmax = 150c, v ja = 43c/w, v jc = 5c/w exposed pad ( pin 15) is pgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 comp fb snsgnd run v in sw1 bst1 pgnd 16 15 14 13 12 11 10 9 sgnd pwm/sync v cc nc v out sw2 bst2 pgnd top view 17 pgnd mse package 16-lead plastic msop t jmax = 150c, v ja = 40c/w, v jc = 10c/w exposed pad ( pin 17) is pgnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc3111ede#pbf ltc3111ede#trpbf 3111 14-lead (4mm w 3mm) plastic dfn C40c to 125c ltc3111ide#pbf ltc3111ide#trpbf 3111 14-lead (4mm w 3mm) plastic dfn C40c to 125c ltc3111hde#pbf ltc3111hde#trpbf 3111 14-lead (4mm w 3mm) plastic dfn C40c to 150c ltc3111mpde#pbf ltc3111mpde#trpbf 3111 14-lead (4mm w 3mm) plastic dfn C55c to 150c ltc3111emse#pbf ltc3111emse#trpbf 3111 16-lead plastic msop C40c to 125c ltc3111imse#pbf ltc3111imse#trpbf 3111 16-lead plastic msop C40c to 125c ltc3111hmse#pbf ltc3111hmse#trpbf 3111 16-lead plastic msop C40c to 150c ltc3111mpmse#pbf ltc3111mpmse#trpbf 3111 16-lead plastic msop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range ( notes 2, 5) ltc 3 111 e, ltc 3111 i ........................... C 40 c to 125 c ltc 3 111 h ........................................... C 40 c to 150 c ltc 3 111 mp ........................................ C 55 c to 15 0 c maximum junction temperature ( note 3) ............. 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ms op ............................................................... 30 0 c ltc 3111 3111fa for more information www.linear.com/ltc3111
3 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = v out = pwm /sync = run = 5v unless otherwise noted. parameter condition min typ max units input operating range l 2.5 15 v v in uvlo threshold rising l 1.9 2.1 2.3 v v in uvlo hysteresis 200 mv v cc uvlo threshold rising l 2.2 2.35 2.5 v v cc uvlo hysteresis 190 mv output voltage adjust range l 2.5 15 v intv cc clamp voltage v in = 5v or 15v l 3.9 4.2 4.5 v quiescent currentburst mode operation fb = 1v, pwm /sync = 0v 55 80 a quiescent currentshutdown run = v out = v cc = 0v, not including switch leakage 0 1 a feedback voltage pwm operation l 0.78 0.8 0.82 v feedback leakage fb = 0.8v 0 50 na nmos switch leakage switches a, b, c, d, v in = v out = 15v 0.5 5 a nmos switch on-resistance switch a 90 m switch b, c, d 105 m input current limit l 2.3 3 3.7 a peak current limit 5.8 a burst current limit pwm /sync = 0v 0.8 a burst zero current threshold pwm /sync = 0v 0.1 a reverse current limit C1 a maximum duty cycle percentage of the period sw2 is low in boost mode (note 7) l 85 90 % minimum duty cycle percentage of the period sw1 is low in buck mode (note 7) l 0 % sw1, sw2 minimum low time (note 7) 160 ns frequency pwm /sync = 5v l 700 800 900 khz sync frequency range (note 6) l 600 1500 khz pwm /sync threshold l 0.5 0.9 1.5 v run threshold to enable v cc rising l 0.35 0.8 1.15 v run threshold to disable v cc falling l 0.3 v run threshold to enable switching rising l 1.15 1.18 1.23 v run hysteresis 120 mv note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetimes. note 2: the ltc3111 is tested under pulsed load conditions such that t j t a . the ltc3111e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3111i is guaranteed to meet performance specifications from C40c to 125c junction temperature, the ltc3111h is guaranteed to meet performance specifications from C40c to 150c junction temperature and the ltc3111mp is guaranteed and tested to meet performance specifications from C55c to 150c junction temperature. high junction temperatures degrade operating lifetimes: operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. ltc 3111 3111fa for more information www.linear.com/ltc3111
4 typical performance characteristics maximum output current in pwm mode vs v in maximum load current in burst mode operation vs v in wide v in to 5v out efficiency wide v in to 5v out power loss wide v in to 3.3v out efficiency wide v in to 3.3v out power loss electrical characteristics note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: voltage transients on the switch pins beyond the dc limit specified in the absolute maximum ratings, are non-disruptive to normal operation when using good layout practices, as shown on the demo board or described in the data sheet and application notes. note 5: the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 6: sync frequency range is tested with a square wave. operation with 100ns minimum high or low time is assured by design. note 7: switch timing measurements are made in an open-loop test configuration . t iming in the application may vary somewhat from these values due to differences in the switch pin voltage during the non-overlap durations when the switch pin voltage is influenced by the magnitude and direction of the inductor current. t a = 25c, v in = 5v, v out = 5v, unless otherwise specified v in (v) 2 0 maximum output current (a) 0.2 0.6 0.8 1.0 8 9 10 1211 1413 2.0 1.8 3111 g01 0.4 3 4 5 6 7 15 1.2 1.4 1.6 v out = 3.3v, l = 4.7h v out = 5v, l = 6.8h v out = 12v, l = 10h input current limit = 2.3a v in (v) 2 3 4 maximum output current (ma) 400 600 3111 g02 200 0 5 6 7 8 9 10 11 12 13 14 15 800 300 500 100 700 v out = 3.3v v out = 5v v out = 12v load current (a) 60 50 efficiency (%) 80 100 40 70 90 0.0001 0.01 0.1 1 10 3111 g03 30 0.001 v in = 2.7v v in = 5v v in = 12v burst pwm load current (a) 0.0001 0.001 0.0001 0.001 power loss (w) 0.1 10 0.01 0.1 1 10 3111 g04 0.01 1 v in = 2.7v v in = 5v v in = 12v burst pwm load current (a) 0.0001 0.001 70 efficiency (%) 80 90 100 0.01 1 0.1 3111 g05 60 50 40 30 v in = 2.7v v in = 5v v in = 12v burst pwm load current (a) 0.01 power loss (w) 0.1 1 10 0.01 0.1 1 3111 g06 0.0001 0.001 0.0001 0.001 v in = 2.7v v in = 5v v in = 12v burst pwm ltc 3111 3111fa for more information www.linear.com/ltc3111
5 typical performance characteristics 800khz pwm mode no-load input current burst mode no-load current with v cc from v in or back-fed from v out with an optional diode v cc voltage vs v in pwm mode no load v cc voltage vs v cc current normalized n-channel mosfet resistance vs v cc wide v in to 12v out efficiency t a = 25c, v in = 5v, v out = 5v, unless otherwise specified wide v in to 12v out power loss 12v in to 12v out efficiency at f = 600khz, 800khz, 1mhz and 1.5mhz with l = 10h load current (a) 0.0001 0.001 70 efficiency (%) 80 90 100 0.01 1 0.1 3111 g07 60 50 40 30 v in = 2.7v v in = 5v v in = 12v pwm burst load current (a) 0.0001 0.001 0.0001 0.001 power loss (w) 0.1 10 0.01 0.1 1 10 3111 g08 0.01 1 v in = 2.7v v in = 5v v in = 12v burst pwm load current (a) 70 efficiency (%) 80 90 100 0.01 1 0.1 3111 g09 60 50 40 30 f = 600khz f = 800khz f = 1mhz f = 1.5mhz v in (v) 2 v in current (ma) 12 16 20 12 31111 g10 8 4 10 14 18 6 2 0 4 6 8 3 13 5 7 11109 14 15 v in (v) 2 0 v in current (a) 50 150 200 250 9 10 11 12 13 14 450 3111 g11 100 43 5 6 7 8 15 300 350 400 v cc from v in v cc from v out v out = 5v v in (v) 2 v cc voltage (v) 3.7 4.1 4.5 7 3 8 4 9 5 10 6 11 3111 g12 3.3 2.9 3.5 3.9 4.3 3.1 2.7 2.5 12 13 14 15 current from v cc (ma) 0 v cc (v) 3.9 4.0 4.1 60 70 30 40 50 3111 g13 3.8 3.7 10 20 80 3.6 3.5 4.2 v cc (v) 2.5 normalized mosfet resistance 1.05 1.10 1.15 4.0 5.0 3111 g14 1.00 0.95 0.90 3.0 3.5 4.5 1.20 1.25 1.30 normalized n-channel mosfet resistance vs temperature temperature (c) ?50 0.6 normalized mosfet resistance 0.7 0.9 1.0 1.1 1.6 1.3 0 50 3111 g15 0.8 1.4 1.5 1.2 100 150 ltc 3111 3111fa for more information www.linear.com/ltc3111
6 typical performance characteristics run threshold to enable/disable v cc vs v in pwm mode input, peak and reverse current limits vs temperature burst mode peak current, i zero limits vs temperature feedback pin program voltage vs temperature run threshold to enable/disable v cc vs temperature v cc and v in uvlo voltage thresholds vs temperature run threshold to enable/disable switching vs v in t a = 25c, v in = 5v, v out = 5v, unless otherwise specified temperature (c) ?50 feedback pin program voltage (mv) 798.5 799.0 799.5 150 3111 g16 798.0 797.5 796.5 0 50 100 797.0 800.5 800.0 temperature (c) ?50 v cc and v in uvlo thresholds (v) 2.0 2.1 2.2 150 3111 g17 1.9 1.8 1.7 1.5 0 50 100 1.6 2.4 2.3 v cc uvlo rising v in uvlo rising v cc uvlo falling v in uvlo falling v in (v) 2 run threshold to enable v cc (v) 0.80 0.90 1.00 10 3111 g18 0.70 0.60 0.75 0.85 0.95 0.65 0.55 0.50 4 6 8 12 3 11 5 7 9 13 14 15 rising falling temperature (c) ?50 0.50 run thresholds to enable v cc (v) 0.55 0.65 0.70 0.75 1.00 0.85 0 50 3111 g19 0.60 0.90 0.95 0.80 100 150 rising falling v in (v) 2 run threshold to enable switching (v) 1.10 1.05 1.30 1.25 10 3111 g20 1.20 1.15 1.00 4 6 8 12 3 11 5 7 9 13 14 15 rising falling temperature (c) ?50 run pin threshold to enable switching (v) 1.10 1.05 1.20 1.30 100 3111 g21 1.15 1.25 1.00 0 50 150 rising falling temperature (c) ?50 i limit , i peak and i reverse (a) 2 3 4 150 3111 g22 1 0 ?2 0 50 100 ?1 6 5 peak current limit input current limit reverse current limit temperature (c) ?50 0 50 100 150 i lmit , i peak , and i reverse (a) 0.6 0.8 1.0 3111 g23 0.4 0.2 0.5 0.7 0.9 0.3 0.1 0 i zero peak current limit run threshold to enable/disable switching vs temperature ltc 3111 3111fa for more information www.linear.com/ltc3111
7 typical performance characteristics 5v in to 5v out burst to pwm response 12v in to 5v out burst mode v out ripple 12v in to 5v out pwm v out ripple 7.5v in to 5v out start-up response 1.5mhz sync signal capture and release 12v in to 5v out sw1 and sw2 waveforms 3v in to 5v out 0.05a to 0.25a load response 5v in to 5v out 0.05a to 0.5a load response 12v in to 5v out 0.05a to 0.5a load response t a = 25c, v in = 5v, v out = 5v, unless otherwise specified v out 200mv/div inductor current 500ma/div load current 200ma/div 500s/div front page application 3111 g24 v out 200mv/div inductor current 500ma/div load current 500ma/div 500s/div front page application 3111 g25 v out 500mv/div inductor current 1a/div load current 500ma/div 500s/div front page application 3111 g26 v out 200mv/div pwm/sync 5v/div inductor current 500ma/div 500s/div i load = 10ma l = 4.7h c out = 22f 3111 g27 v out 200mv/div inductor current 500ma/div 20s/div i load = 50ma l = 4.7h c out = 22f 3111 g28 v out 50mv/div inductor current 500ma/div 1s/div i load = 500ma l = 4.7h c out = 22f 3111 g29 v out 2v/div inductor current 1a/div run 5v/div 500s/div i load = 500ma l = 4.7h c out = 22f 3111 g30 inductor current 500ma/div pwm/sync 5v/div v out 200mv/div 100s/div 3111 g31 inductor current 500ma/div sw1 10v/div sw2 5v/div 1s/div 3111 g32 ltc 3111 3111fa for more information www.linear.com/ltc3111
8 typical performance characteristics 3.3v out die temperature rise vs continuous load current 4-layer demo board at 25c 5v out die temperature rise vs continuous load current 4-layer demo board at 25c 12v out die temperature rise vs continuous load current 4-layer demo board at 25c sw1, sw2 minimum low time vs v cc sw1, sw2 minimum low time vs temperature v out short-circuit response and recovery v cc short-circuit response and recovery t a = 25c, v in = 5v, v out = 5v, unless otherwise specified inductor current 1a/div v out 2v/div 1ms/div 3111 g33 inductor current 1a/div v cc 5v/div v out 2v/div 1ms/div 3111 g34 soft-start load current (a) 0 die temperature rise (c) 30 40 50 1.6 3111 g35 20 10 25 35 45 15 5 0 0.4 0.8 1.2 0.2 1.8 0.6 1.0 1.4 2.0 v in = 2.7v v in = 12v v in = 5v load current (a) 0 die temperature (c) 20 40 60 10 30 50 0.4 0.8 1.2 1.6 3111 g36 2.0 0.20 0.6 1.0 1.4 1.8 v in = 2.7v v in = 12v v in = 5v load current (a) 0 die temperature rise (c) 40 50 60 1.81.6 3111 g37 30 20 0 0.4 0.8 1.2 0.2 2.0 0.6 1.0 1.4 10 80 70 v in = 2.7v v in = 12v v in = 5v v cc (v) 2 0 sw1, sw2 minimum low time (ns) 50 100 150 200 300 2.5 3 3.5 4 3111 g38 4.5 5 250 i load = 300ma sw1, v in = 4v sw2, v in = 6v temperature (c) ?50 50 sw1, sw2 minimum low time (ns) 70 110 130 150 250 190 0 50 3111 g39 90 210 230 170 100 150 i load = 300ma sw1, v in = 4v sw2, v in = 6v ltc 3111 3111fa for more information www.linear.com/ltc3111
9 pin functions (dfn/msop) comp (pin 1/pin 1): error amp output. an r-c network connected from this pin to fb sets the loop compensa- tion for the voltage converter. refer to the applications information section for component selection details. fb (pin 2/pin 2): feedback voltage input. connect the v out resistor divider tap to this pin. the output voltage can be adjusted from 2.5v to 15v by the following equation: v out = 0.8v ? 1 + r1 r2 ? ? ? ? ? ? where r1 is the resistor between v out and fb and r2 is the resistor between fb and gnd snsgnd (pin 3/pin 3): this pin must be connected to ground. run ( pin 4/pin 4): input to enable or disable the ic and set custom input undervoltage lockout ( uvlo) thresholds. the run pin can be driven by an external logic signal to enable and disable the ic. in addition, the voltage on this pin can be set by a resistive voltage divider connected to the input supply in order to provide accurate turn-on and turn-off (uvlo) thresholds determined by: v in(run) = 1.2v ? 1 + r5 r6 ? ? ? ? ? ? the ic is enabled if run exceeds 1.2 v nominally. once enabled, the uvlo threshold has a built-in hysteresis of approximately 120 mv, turn- off will occur when the voltage on run drops to below 1.08 v nominally. to continuously enable the ic, run can be tied directly to the input voltage up to the absolute maximum rating. this pin should not be left unconnected. v in (pin 5/pin 5): input supply voltage. this pin should be bypassed to the ground plane with at least 10 f of low esr, low esl ceramic capacitance. place this capacitor as close to the pin as possible and provide as short a return path to the ground plane as possible. sw1 (pin 6/pin 6): the external inductor and internal switches a and b are connected here. bst1 (pin 7/pin 7): boosted floating driver supply for a-switch driver. connect a 0.1 f capacitor from this pin to sw1. bst2 (pin 8/pin 10): boosted floating driver supply for d-switch driver. connect a 0.1 f capacitor from this pin to sw2. sw2 (pin 9/pin 11): the external inductor and internal switches c and d are connected here. v out (pin 10/pin 12): regulated output voltage. this pin should be connected to a low esr ceramic capacitor. the capacitor should be placed as close to the pin as possible and have a short return to the ground plane. nc (pin 11/pin 13): not connected. this pin should be connected to ground. v cc (pin 12/pin 14): external capacitor connection for the regulated v cc supply. this supply is used to operate internal circuitry and switch drivers. v cc will track v in up to 4.2 v typical, but will maintain this voltage when v in > 4.2v. connect a 1 f ceramic capacitor from this pin to gnd. this pin can be tied to an external supply up to 5.5v. refer to the operation section of this data sheet under power v cc from an external source for more details. pwm /sync (pin 13/pin 15): burst mode control and synchronization input. a dc voltage < 0.5 v commands burst mode operation independent of load current , >1.5v commands 800 khz fixed frequency mode. a digital pulse train between 600 khz and 1.5 mhz applied to this pin will override the internal oscillator and set the operating fre - quency. the pulse train should have a minimum high time or low time greater than 100ns ( note?6). note the ltc3111 has reduced power capability when operating in burst mode operation. this pin should not be left unconnected. sgnd (pin 14/pin 16): signal ground. terminate the run input voltage divider and output voltage divider to sgnd. pgnd ( exposed pad pin 15/pin 8, 9, exposed pad pin?17) power ground. the exposed pad must be soldered to the pcb and electrically connected to ground through the shortest and lowest impedance connection possible. ltc 3111 3111fa for more information www.linear.com/ltc3111
10 simplified block diagram + ? error amp pwm/sync comp fb gnd 0.8v v in v cc ?1a v out soft-start ramp 3111 bd 800k oscillator 4.2v regulator/ clamp reference burst mode operation pll + + ? + ? + ? i limit i peak i zero adrv bdrv v cc cdrv ddrv logic reverse i lim drivers + ? + ? v cc start v in uvlo v cc uvlo run run stop bst1 bst2 v in v out sw1 sw2 4.7h v cc 0.8v 1.2v 3a 5.8a 0.1a + ? + ? 2.1v start 1.2v v in + ? 2.35v + ? + ? bdrv adrv v cc v cc c out v cc cdrv ddrv gnd c in ltc 3111 3111fa for more information www.linear.com/ltc3111
11 operation introduction the ltc3111 is an extended input and output range, syn- chronous 1.5 a buck -boost dc/dc converter optimized for a variety of applications. the ltc3111 utilizes a proprietary switching algorithm, which allows its output voltage to be regulated above, below or equal to the input voltage. the error amplifier output on comp determines the output duty cycle of the switches. the low r ds(on) , low gate charge synchronous switches provide high efficiency pulse width modulation control. high efficiency is achieved at light loads when burst mode operation is commanded. low noise fixed frequency operation oscillator, phase lock loop an internal oscillator circuit sets the normal frequency of operation to 800 khz. a pulse train applied to the pwm / sync pin allows the operating frequency to be programmed between 600khz to 1.5mhz via an internal phase- lock- loop circuit. the pulse train must have a minimum high or low state of at least 100 ns to guarantee operation ( see note ?6 of the electrical characteristics). error amplifier the ltc3111 contains a high gain operational amplifier which provides frequency compensation of the control loop to maintain output voltage regulation. to ensure loop stability, an external compensation network must be installed in the application circuit. a type iii compensation network, as shown in figure 1, is recommended for most applications since it provides the flexibility to optimize the converters transient response while simultaneously minimizing any dc error in the output voltage. as shown in figure 1, the error amplifier is followed by an internal analog divider which adjusts the loop gain by the reciprocal of the input voltage when the converter is in buck mode and by the output voltage when the converter is in boost mode which minimizes loop-gain variation over changes in the input voltage. this simplifies design of the compensation network and optimizes the transient response over the entire range of input voltages. details v in 0.8v 3111 f01 fb ltc3111 c fb c ff r ff r1 r2 c pole r fb v out comp v out sgnd sw1 sw2 + ? pwm comparators figure 1. error amplifier and compensation network on designing the compensation network for the ltc3111 applications can be found in the applications information section of this data sheet. current limit operation the buck-boost converter has two current limit circuits. the input current limit sources current into the feedback divider network whenever the current in switch a exceeds 3a typical. due to the high gain of the feedback loop, the injected current forces the error amplifier output to decrease until the average current through switch a decreases ap - proximately to the current limit value. the input current limit utilizes the error amplifier in an active state and thereby provides a smooth recovery with little overshoot once the current limit fault condition is removed. since the current limit is based on the average current through switch a, the peak inductor current in current limit will have a dependency on the duty cycle ( i.e., on the input and output voltages) in the overcurrent condition. for this current limit feature to be most effective, the thevenin resistance from the fb to ground should exceed 100k. the speed of the input current limit circuit is limited by the dynamics of the converter loop. on a hard output short, it i s possible for the inductor current to increase substantially beyond the input current limit before the input current limit circuit can react. for this reason, there is a peak current limit circuit which turns off switch a if the current in switch a exceeds approximately 190% of the input current limit value. this provides additional protection in the case of an instantaneous hard output short. ltc 3111 3111fa for more information www.linear.com/ltc3111
12 operation should the output voltage become shorted, the input current limit is reduced to approximately one half of the normal operating current limit. reverse current limit during fixed frequency operation, a reverse current com - parator on switch d monitors the current entering the v out pin. when this current exceeds 1a ( typical) switch d will be turned off for the remainder of the switching cycle. this feature protects the buck-boost converter from excessive reverse current if the buck-boost output is held above the regulation voltage. internal soft-start the ltc3111 buck-boost converter has an independent internal soft-start circuit with a nominal duration of 2ms. the converter remains in regulation during soft-start and will therefore respond to output load transients which occur during this time. in addition, the output voltage rise time has minimal dependency on the size of the output capacitor or load current during start- up. soft - start is reset during a thermal shutdown. thermal considerations for the ltc3111 to provide maximum output power, it is imperative that a good thermal path be provided to dis - sipate the heat generated within the package. this can be accomplished by taking advantage of the large thermal pad on the underside of the ic. it is recommended that multiple vias in the printed circuit board be used to conduct the heat away from the ic and into a copper plane with as much area as possible. the efficiency and maximum output current capability of the ltc3111 will be reduced if the converter is required to continuously deliver large amounts of power or oper - ate at high temperatures. the amount of output current derated is dependent upon factors such as board ground plane or heat sink area, ambient operating temperature and the input/output voltages of the application. a poor thermal design can cause excessive heating, resulting in impaired performance or reliability. the temperature rise curves given in the typical perfor - mance characteristics section can be used as a guide to predict junction temperature rise from ambient. these curves were generated by mounting the ltc3111 to the 4-layer fr-4 demo printed circuit board layout shown in figure 4. the curves were taken at room temperature, elevated ambient temperature will result in greater ther - mal rise rates due to increased r ds(on) of the n-channel mosfets with temperature. the die temperature of the ltc3111 should be kept below the maximum junction rating of 125 c for e- and i-grades and 150 c for h- and mp-grades. in the event that the junction temperature gets too high (approximately 170 c), the input current limit will be linearly decreased from its typical value. if the junction temperature continues to rise and exceeds approximately 175c the ltc3111 will be disabled. all power devices are turned off and all switch nodes put to a high imped - ance state. the soft-start circuit for the converter is reset during thermal shutdown to provide a smooth recovery once the overtemperature condition is eliminated. when the die temperature drops to approximately 170 c the ltc3111 will restart. undervoltage lockouts the ltc3111 buck-boost converter is disabled and all power devices are turned off until the v cc supply reaches 2.35v ( typical). the soft-start circuit is reset during under- voltage lockout to provide a smooth restart once the input voltage rises above the undervoltage lockout threshold. a second uvlo circuit disables all power devices if v in is below 2.1 v rising, 1.9 v falling ( typical). this can provide a lower v in operating range in applications where v cc is powered from an alternate source or v out after start-up. inductor damping when the ltc3111 is disabled (run = 0 v) or sleeping during burst mode operation ( pwm /sync = 0 v), active circuits damp the inductor voltage through 1k (typical) impedance between sw1 and sw2 and gnd to reduce ringing and emi. ltc 3111 3111fa for more information www.linear.com/ltc3111
13 operation pwm mode operation when the pwm /sync pin is held high, the ltc3111 buck- boost converter operates in a fixed-frequency pulse-width modulation ( pwm ) mode using voltage mode control. full output current is only available in pwm mode. a proprietary switching algorithm allows the converter to transition between buck, buck-boost, and boost modes without discontinuity in inductor current. the switch topology for the buck-boost converter is shown in figure 2. this switching algorithm provides a seamless transition between operating modes and eliminates discontinuities in average inductor current, inductor current ripple, and loop transfer function throughout the operational modes. these advantages result in increased efficiency and stabil - ity in comparison to the traditional 4- switch buck-boost converter. output vol tage programming the output voltage is set via the external resistor divider comprised of resistors r1 and r2 as show in figures 1. the resistor divider values determine the output regulation voltage according to: v out = 0.8v ? 1 + r1 r2 ? ? ? ? ? ? in addition to setting the output voltage, the value of r1 is instrumental in controlling the dynamics of the compensa - tion network . when changing the value of this resistor, care must be taken to understand the impact this will have on the compensation network. in addition, the thevenin equivalent resistance of the resis - tor divider controls the gain of the input current limit. to maintain sufficient gain in this loop, it is recommended that the thevenin resistance be greater than 100k. run comparator in addition to serving as a logic-level input to enable the ic, the run pin includes an accurate internal comparator that allows it to be used to set custom rising and falling on/off thresholds with the addition of an external resistor divider. when run is driven above its logic threshold (0.8 v typi - cal), the ldo regulator is enabled, which provides power to the internal control circuitry of the ic. if the voltage on run is increased further so that it exceeds the run comparator accurate analog threshold (1.2 v typical), all functions of the buck-boost converter will be enabled and a start-up sequence will ensue. if run is brought below the accurate comparator threshold , the buck-boost converter will inhibit switching, but the a l v in v out b 3111 f02 d c figure 2. buck-boost switch topology when the input voltage is significantly greater than the output voltage, the buck-boost converter operates in buck mode. switch d turns on at maximum duty cycle and switch?c turns on just long enough to refresh the voltage on the bst2 capacitor used to drive switch d. switches a and b are pulse-width modulated to produce the required duty cycle to support the output regulation voltage. as the input voltage nears the output voltage, switches?a and d are on for a greater portion of the switching pe - riod, providing a direct current path from v in to v out . switches?b and c are turned on only enough to ensure proper regulation and/or provide charging of the bst1 and bst2 capacitors. the internal control circuitry will determine the proper duty cycle in all modes of operation, which will vary with load current. as the input voltage drops well below the output voltage, the converter operates solely in boost mode. switch a turns on at maximum duty cycle and switch b turns on just long enough to refresh the voltage on the bst1 ca - pacitor used to drive a. switches c and d are pulse-width modulated to produce the required duty cycle to regulate the output voltage. ltc 3111 3111fa for more information www.linear.com/ltc3111
14 operation ldo regulator and control circuitry will remain powered unless run is brought below its logic threshold. therefore , in order to completely shut down the ic, it is necessary to ensure that run is brought below its worst-case low logic threshold of 0.3 v. run is a high voltage input and can be tied directly to v in to continuously enable the ic when the input supply is present. the run pin can be driven above v in or v out as long as it stays within the operating range of 15v. with the addition of an optional resistor divider as shown in figure 3, the run pin can be used to establish a user- programmable turn on and turn off threshold. powering v cc from an external source the ltc3111s v cc regulator can be powered or back-fed from an external source up to 5.5 v. the advantage of back feeding v cc from a voltage above 4.2 v is higher efficiency. for 5v out applications, v cc can be easily powered from v out using an external low current schottky as shown in several applications circuits in the typical applications section. back feeding v cc also improves a light load pwm mode output voltage ripple that occurs when the inductor passes through zero current by reducing the switch pin anti-cross conduction times. a disadvantage of powering v cc from v out is that no-load quiescent current increases at lower input voltage in burst mode operation as shown in the typical performance characteristics ( compared to v cc powered from v in ). burst mode operation when the pwm /sync pin is held low, the buck-boost converter operates utilizing a variable frequency switch - ing algorithm designed to improve efficiency at light load and reduce the standby current at zero load. in burst mode operation, the inductor is charged with fixed peak amplitude current pulses and as a result only a fraction of the maximum output current can be delivered when in burst mode operation. these current pulses are repeated as often as necessary to maintain the output regulation voltage. the maximum output current, i max , which can be supplied in burst mode operation is dependent upon the input and output voltage as approximated by the following formula: i max = i pk 2 ? ? v in v in + v out ? ? ? ? ? ? a where i pk is the burst mode peak current limit (0.8 a typi- cal) in amps and is the efficiency. if the buck-boost load exceeds the maximum burst mode current capability, the output rail will lose regulation. in burst mode operation, the error amplifier is configured for low power operation and used to hold the compensation pin, comp, to reduce transients that may occur during transitions from and to burst and pwm mode operation. + ? enable switching 1.2v ltc3111 3111 f03 v in run r5 r6 accurate threshold + ? enable switching ldo and control circuits 0.8v logic threshold figure 3. accurate run comparator the buck-boost converter is enabled when the voltage on run reaches 1.2v ( nominal). therefore, the turn-on voltage threshold on v in is given by: v in(run) = 1.2v ? 1 + r5 r6 ? ? ? ? ? ? once the converter is enabled, the run comparator in- cludes a built-in hysteresis of approximately 120 mv, so that the turn- off threshold will be approximately 10% lower than the turn-on threshold. put another way, the internal threshold level for the run comparator looks like 1.08v after the ic is enabled. the run comparator is relatively noise insensitive, but there may be cases due to pcb layout, very large value resistors for r5 and r6 or proximity to noisy components where noise pickup is unavoidable and may cause the turn-on or turn-off of the ic to be intermittent. in these cases, a filter capacitor can be added across r6 to ensure proper operation. ltc 3111 3111fa for more information www.linear.com/ltc3111
15 applications information the basic ltc3111 application circuit is shown on the front page of this data sheet. the external component selection is dependent upon the required performance of the ic in each particular application given trade-offs such as pcb area, output voltages, output currents, ripple voltages, and efficiency. this section of the data sheet provides some basic guidelines and considerations to aid in the selection of external components and the design of the application circuit. inductor selection to achieve high efficiency, a low esr inductor should be utilized for the buck- boost converter. in addition, the buck- boost inductor must have a saturation current rating that is greater than the worst-case average inductor current plus half the ripple current. the peak-to-peak inductor current ripple for buck or boost mode operation can be calculated from the following formulas: ? i l(p-p_buck) = v out l ? v in C v out v in ? ? ? ? ? ? ? 1 f C t low ? ? ? ? ? ? ? i l(p-p_boost) = v in l ? v out C v in v out ? ? ? ? ? ? ? 1 f C t low ? ? ? ? ? ? where f is the frequency in hz and l is the inductance in henries and t low is the switch pin minimum low time in seconds, which is typically 160ns. in addition to affecting output current ripple, the inductor value can also impact the stability of the feedback loop. in boost mode, the converter transfer function has a right- half-plane zero at a frequency that is inversely proportional to the value of the inductor. as a result, a large inductance can move this zero to a frequency that is low enough to degrade the phase margin of the feedback loop. it is rec - ommended that the inductor value be chosen less than 15h if the converter is to be used in the boost region. for 800 khz operation, a 4.7 h inductor is recommended for 5v out and 10h for 12v out . the inductor dc resistance can impact the efficiency of the buck-boost converter as well as the maximum output current capability at low input voltage. in buck mode, the output current is limited only by the inductor current reaching the current limit value. however, in boost mode, especially at large step-up ratios, the output current capa- bility can also be limited by the total resistive losses in the power stage. these include switch resistances, inductor resistance, and pcb trace resistance. use of an inductor with high dc resistance can degrade the output current capability from that shown in the graph in the typical performance characteristics section of this data sheet. different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. shielded construction is generally preferred as it minimizes the chances of interference with other circuitry. the choice of inductor style depends upon the price, sizing, and emi requirements of a particular application. table 1 provides a small sampling of inductors that are well suited to many ltc3111 buck-boost converter ap - plications. within each family ( i.e., at a fixed size), the dc resistance generally increases and the maximum current generally decreases with increased inductance. table 1. representative buck-boost surface mount inductors part number value (h) dcr (m) max dc current (a) size (mm) w l h coilcraft lps6225 lps6235 4.7 6.8 65 75 3.2 2.8 6.2 6.2 2.5 6.2 6.2 3.5 cooper -bussmann fp3-8r2-r cd1-150-r 8.2 15 74 50 3.4 3.6 7.3 6.7 3.0 10.5 10.4 4.0 sumida cdrh8d28/hp cdrh8d28np 10 4.7 78 24.7 3.0 3.4 8.3 8.3 3.0 8.3 8.3 3.0 toko b1047as-6r8n b1179bs-150m 6.8 15 36 56 2.9 2.7 7.6 7.6 5.0 12.0 12.0 6.0 w rth 7447789004 744311470 4.7 4.7 33 19.5 2.9 6 7.3 7.3 3.2 6.9 6.9 3.8 output capacitor selection a low esr output capacitor should be utilized at the buck-boost converter output in order to minimize output voltage ripple. multilayer x5r and x7r dielectric ceramic capacitors are an excellent choice as they have low esr and are available in small footprints. the capacitor should be ltc 3111 3111fa for more information www.linear.com/ltc3111
16 applications information chosen large enough to reduce the output voltage ripple to acceptable levels. the minimum output capacitor needed for a given output voltage ripple ( neglecting the capacitor esr and esl) can be calculated by the following formulas: ? v p-p buck ( ) = i load ? t low c out ? v p-p boost ( ) = i load f ?c out ? v out C v in + t low ? f ? v in v out ? ? ? ? ? ? where f is the frequency in hz, c out is the output capaci- tance in f, i load is the output current in amps and t low is the switch pin minimum low time in seconds, which is typically 160ns. in addition to output ripple generated across the output capacitor, there is also output ripple produced across the internal resistance of the output capacitor. the esr- generated output voltage ripple is proportional to the series resistance of the output capacitor and is given by the following expression: ? v p-p buck ( ) = i load ?r esr 1C t low ? f ? i load ?r esr ? v p-p boost ( ) = i load ?r esr ? v out v in 1C t low ? f ( ) ? i load ?r esr ? v out v in where r esr is the series resistor of the output capacitor and all other terms are as previously defined. input capacitor selection it is recommended that a low esr ceramic capacitor with a value of at least 10 f be located as close to the v in pin as possible. in addition, the return trace from the pin to the ground plane should be made as short as possible. it is important to minimize any stray resistance from the converter to the battery or power source. if cabling is required to connect the ltc3111 to the battery or power supply, a higher esr capacitor or a series resistor with a low esr capacitor in parallel with the low esr capacitor may be required to damp out ringing caused by the cable inductance. capacitor vendor information both the input bypass capacitors and output capacitors used with the ltc3111 must be low esr and designed to handle the large ac currents generated by switching converters. this is important to maintain proper functioning of the ic and to reduce input/output ripple. many modern low voltage ceramic capacitors experience significant loss in capacitance from their rated value with increased dc bias voltages. for example, it is not uncommon for a small surface mount ceramic capacitor to lose more than 50% of its rated capacitance when operated near its rated voltage. as a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a larger case size than required in order to actually realize the intended capacitance at the full operating voltage. for details, con - sult the capacitor vendors curve of capacitance versus dc bias voltage. the capacitors listed in table 2 provide a sampling of small surface mount ceramic capacitors that are well suited to ltc3111 application circuits. all listed capacitors are either x5r or x7r dielectric in order to ensure that capacitance loss over temperature is minimized. table 2. representative bypass and output capacitors part number value (f) volt age (v) size (mm) l w h (footprint) avx 12103d226 mat 2a 22 25 3.2 2.5 2.79 x5r ceramic kemet c220x226k3ractu a700d226m016 ate 030 22 22 25 16 5.7 5.0 2.4 x7r ceramic 7.3 4.3 2.8 al poly, 25m murata grm32er71e226ke15l 22 25 3.2 2.5 2.5 x7r ceramic panasonic ecj-4yb1e226m 22 25 3.2 2.5 2.5 x5r ceramic sanyo 25svpf47m 47 25 6.6 6.6 5.9 os-con, 30m vishay 94svpd476x0035f12 47 35 10.3 10.3 12.6 os-con, 30m ltc 3111 3111fa for more information www.linear.com/ltc3111
17 applications information pcb layout considerations the ltc3111 switches large currents at high frequencies. special attention should be paid to the pcb layout to en - sure a stable, noise-free and efficient application circuit. figure 4 presents a representative pcb layout to outline some of the primary considerations. a few key guidelines are outlined below: 1. all cir culating high current paths should be kept as short as possible. this can be accomplished by keeping the routes to all circled components in the figure below as short and as wide as possible. capacitor ground connections should via down to the ground plane in the shortest route possible. the bypass capacitors on v in should be placed as close to the ic as possible and should have the shortest possible paths to ground. 2. the exposed pad is the power ground connection for the ltc3111. multiple vias should connect the back pad directly to the ground plane. in addition maximi - zation of the metallization connected to the back pad will improve the thermal environment and improve the power handling capabilities of the ic. 3. the circled components and their connections should all be placed over a complete ground plane to minimize loop cross-sectional areas. this minimizes emi and reduces inductive drops. 4. connections to all of the circled components should be made as wide as possible to reduce the series resistance . this will improve efficiency and maximize the output current capability of the buck-boost converter. thermal and pgnd vias figure 4a. top and fabrication layer of example pcb figure 4b. bottom and fabrication layer of example pcb c out c bst1 c bst2 c in ltc 3111 3111fa for more information www.linear.com/ltc3111
18 5. to prevent large circulating currents from disrupting the output voltage sensing, the ground for each resistor divider should be returned to the ground plane using a via placed close to the ic and away from the power connections. 6. keep the connection from the resistor dividers to the feedback pins ( fb pin) as short as possible and away from the switch pin connections. 7. crossover connections should be made on inner copper layers if available. if it is necessary to place these on the ground plane, make the trace on the ground plane as short as possible to minimize the disruption to the ground plane. buck mode small-signal model the ltc3111 uses a voltage mode control loop to maintain regulation of the output voltage. an externally compen - sated error amplifier drives the comp pin to generate the appropriate duty cycle of the power switches. use of an external compensation network provides the flexibility for optimization of closed-loop performance over the wide variety of output voltages, switching frequencies, and external component values supported by the ltc3111. the small-signal transfer function of the buck-boost con - verter i s different in the buck and boost modes of operation an d care must be ta ken to ensure stability in both operating regions. when stepping down from a higher input voltage to a lower output voltage, the converter will operate in buck mode and the small-signal transfer function from the error amplifier output comp, to the converter output voltage is given by the following equation: v o v comp buck = g buck 1 + s 2 ? ? f z 1 + s 2 ? ? f o ?q + s 2 ? ? f o ? ? ? ? ? ? 2 the gain term, g buck , is comprised of three different components: the gain of the analog divider, the gain of the pulse-width modulator, and the gain of the power stage as given by the following expressions where v in is the input voltage to the converter, f is the switching frequency, r is the load resistance, and t low is the switch pin mini- mum low time, which is typically 160 ns. the parameter r s represents the average series resistance of the power stage and can be approximated as twice the average power switch resistance plus the dc resistance of the inductor. g buck = g divider ?g pwm ?g power g divider = 18 v in g pwm = 2.5 ? 1C t low ? f ( ) g power = v in ?r 1C t low ? f ( ) ? r + r s ( ) notice that the gain of the analog divider cancels the input voltage dependence of the power stage. as a result, the buck mode gain is approximated by a constant as given by the following equation: g buck = 45 ? r r + r s ? 45 = 33db the buck mode transfer function has a single zero which is generated by the esr of the output capacitor. the zero frequency, f z , is given by the following expression where r c and c o are the esr and value of the output filter ca- pacitor respectively. f z = 1 2 ? ?r c ?c o in most applications, an output capacitor with a very low esr is utilized in order to reduce the output voltage ripple to acceptable levels. such low values of capacitor esr result in a very high frequency zero and as a result the zero is commonly too high in frequency to significantly impact compensation of the feedback loop. the denominator of the buck mode transfer function exhibits a pair of resonant poles generated by the lc filtering of the power stage. the resonant frequency of the power stage, f o , is given by the following expression where l is the value of the inductor: f o = 1 2 ? ? r + r s l ?c o r + r c ( ) ? 1 2 ? ? l ?c o applications information ltc 3111 3111fa for more information www.linear.com/ltc3111
19 the quality factor, q, has a significant impact on compen- sation of the voltage loop since a higher q factor produces a sharper loss of phase near the resonant frequency. the quality factor is inversely related to the amount of damping in the power stage and is substantially influenced by the average series resistance of the power stage, r s . lower values of r s will increase the q and result in a sharper loss of phase near the resonant frequency and will require more phase boost or lower bandwidth to maintain an adequate phase margin. q = l ?c o r + r c ( ) ? r + r s ( ) r ?r c ?c o + l + c o ?r s ? r + r c ( ) ? l ?c o l r + c o ?r s boost mode small-signal model when stepping up from a lower input voltage to a higher output voltage, the buck-boost converter will operate in boost mode where the small-signal transfer function from control voltage, v comp , to the output voltage is given by the following expression: v o v comp boost = g boost 1 + s 2 ? ? f z ? ? ? ? ? ? ? 1C s 2 ? ? f rhpz ? ? ? ? ? ? 1 + s 2 ? ? f o ?q + s 2 ? ? f o ? ? ? ? ? ? 2 in boost mode operation, the transfer function is character - ized by a pair of resonant poles and a zero generated by the esr of the output capacitor as in buck mode. however, in addition there is a right-half-plane zero which generates increasing gain and decreasing phase at higher frequen - cies. as a result, the crossover frequency in boost mode operation generally must be set lower than in buck mode in order to maintain sufficient phase margin. the boost mode gain, g boost , is comprised of three components: the analog divider, the pulse width modula- tor and the power stage. the gain of the pw m remains the same as in buck mode operation, but the gain of the analog divider and power stage in boost mode are given by the following equation: g divider = 18 v out g power = v out 2 1C t low ? f ( ) ? v in by combining the individual terms, the total gain in boost mode can be reduced to the following expression. notice that unlike in buck mode, the gain in boost mode is a function of both the input and output voltage: g boost = 45 ? v out v in in boost mode operation, the frequency of the right-half- plane zero, f rhpz , is given by the following expression. the frequency of the right-half-plane zero decreases at higher loads and with larger inductors: f rhpz ? r ? 1C t low ? f ( ) 2 ? v in 2 2 ? ?l ? v out 2 in boost mode, the resonant frequency of the power stage has a dependence on the input and outputvoltage as shown by the following equation: f o = 1 2 ? ? r s + r ? v in 2 v out 2 l ?c o ? r + r c ( ) ? 1 2 ? ? v in v out ? 1 l ?c o finally, the magnitude of the quality factor of the power stage in boost mode operation is given by the following expression: q = l ?c o ?r ? r s + r ? v in 2 v out 2 ? ? ? ? ? ? l + c o ?r s ?r applications information ltc 3111 3111fa for more information www.linear.com/ltc3111
20 applications information compensation of the voltage loop the small-signal models of the ltc3111 reveal that the transfer function from the error amplifier output, comp, to the output voltage is characterized by a set of resonant poles and a possible zero generated by the esr of the output capacitor as shown in the bode plot of figure 5. in boost mode operation, there is an additional right-half- plane zero that produces phase lag and increasing gain at higher frequencies. typically, the compensation network is designed to ensure that the loop crossover frequency is low enough that the phase loss from the right-half-plane zero is minimized. the low frequency gain in buck mode is a constant, but varies with both v in and v out in boost mode. for charging or other applications that do not require an optimized output voltage transient response, a simple type?i compensation network as shown in figure 6 can be used to stabilize the voltage loop. to ensure sufficient phase margin, the gain of the error amplifier must be low enough that the resultant crossover frequency of the control loop is well below the resonant frequency. in most applications, the low bandwidth of the type i com- pensated lo op wi ll not provide sufficient transient response performance. to obtain a wider bandwidth feedback loop, optimize the transient response, and minimize the size of the output capacitor, a type iii compensation network as shown in figure 7 is required. a bode plot of the typical type iii compensation network is shown in figure 8. the type iii compensation network provides a pole near the origin which produces a very high loop gain at dc to minimize any steady-state error in the regulation voltage. tw o zeros located at f zero1 and f zero2 provide sufficient phase boost to allow the loop crossover frequency to be set above the resonant frequency, f o , of the power stage. the type iii compensation network also introduces a second and third pole. the second pole, at frequency f pole2 , reduces the error amplifier gain to a zero slope to prevent the loop crossover from extending 0.8v 3111 f06 fb ltc3111 c1 r1 r2 v out comp sgnd + ? figure 6: error amplifier with type i compensation 0.8v 3111 f07 fb ltc3111 c fb c ff r ff r1 r2 c pole r fb v out comp sgnd + ? figure 7: error amplifier with type iii compensation figure 5: buck-boost converter bode plot gain phase boost mode buck mode ?20db/dec ?40db/dec f o 3111 f05 f rhpz ltc 3111 3111fa for more information www.linear.com/ltc3111
21 applications information too high in frequency. the third pole at frequency f pole3 provides attenuation of high frequency switching noise. the transfer function of the compensated type iii error amplifier from the input of the resistor divider to the output of the error amplifier, comp, is: v comp v o = g comp ? 1 + s 2 ? ? f zero1 ? ? ? ? ? ? ? 1 + s 2 ? ? f zero2 ? ? ? ? ? ? s ? 1 + s 2 ? ? f pole2 ? ? ? ? ? ? ? 1 + s 2 ? ? f pole3 ? ? ? ? ? ? the compensation gain is given by the following equation. the simpler approximate value is sufficiently accurate in most cases since c fb is typically much larger in value than c pole . g comp ? 1 r1? c fb + c pole ( ) ? 1 r1?c fb the pole and zero frequencies of the type iii compensation network can be calculated from the following equations where all frequencies are in hz, resistances are in ohms, and capacitances are in farads. f zero1 = 1 2 ? ?r fb ?c fb f zero2 = 1 2 ? r1 + r ff ( ) ?c ff ? 1 2 ? ?r1?c ff f pole2 = 1 2 ? ? c fb ?c pole c fb + c pole ?r fb ? 1 2 ? ?r fb ?c pole f pole3 = 1 2 ? ?r ff ?c ff in most applications the compensation network is designed so that the loop crossover frequency is above the resonant frequency of the power stage, but sufficiently below the boost mode right - half - plane zero to minimize the additional phase loss. once the crossover frequency is decided upon, the phase boost provided by the compensation network is centered at that point in order to maximize the phase margin. a larger separation in frequency between the zeros and higher order poles will provide a higher peak phase boost but may also increase the gain of the error amplifier which can push out the loop crossover to a higher frequency. the q of the power stage can have a significant influence on the design of the compensation network because it determines how rapidly the 180 of phase loss in the power stage occurs. for very low values of series resistance, r s , the q will be higher and the phase loss will occur sharply. in such cases, the phase of the power stage will fall rapidly to C180 above the resonant frequency and the total phase margin must be provided by the compensation network. f zero1 phase gain ?20db/dec ?20db/dec f zero2 3111 f08 f f pole2 f pole3 figure 8: type iii compensation bode plot ltc 3111 3111fa for more information www.linear.com/ltc3111
22 applications information however, with higher losses in the power stage (larger r s ) the q factor will be lower and the phase loss will occur more gradually. as a result, the power stage phase will not be as close to C180 at the crossover frequency and less phase boost is required of the compensation network. the ltc3111 error amplifier is designed to have a fixed maximum bandwidth in order to provide rejection of switching noise to prevent it from interfering with the control loop. from a frequency domain perspective, this can be viewed as an additional single pole as illustrated in figure 9. the nominal frequency of this pole is 400 khz. for typical loop crossover frequencies below about 60khz the phase contributed by this additional pole is negligible. however, for loops with higher crossover frequencies this additional phase loss should be taken into account when designing the compensation network. the worst-case inductor current ripple to less than 1 a peak to peak. a low esr output capacitor with a value of 22f is specified to yield a worst-case output voltage ripple (occurring at the worst-case step-up ratio and maximum load current) of approximately 20 mv. in summary, the key power stage specifications for this ltc3111 example application are given below. f = 0.8mhz, t low = 160ns v in = 3.5v to 15v v out = 5v at r = 10 c out = 22f, r c = 10m l = 4.7h, r l = 25m r s = 200m with the power stage parameters specified, the compen- sation network can be designed. in most applications, the most challenging compensation corner is boost mode operation at the greatest step-up ratio and highest load current since this generates the lowest frequency right-half-plane zero and results in the greatest phase loss. therefore, a reasonable approach is to design the compensation network at this worst-case corner and then verify that sufficient phase margin exists across all other operating conditions. in this example application, at v in = 3.5v and the full 500 ma load current, the right-half-plane zero will be located at 136 khz and this will be a dominant factor in determining the bandwidth of the control loop. the first step in designing the compensation network is to determine the target crossover frequency for the com - pensated loop. a reasonable starting point is to assume that the compensation network will generate a peak phase boost of approximately 60. therefore, in order to obtain a phase margin of 60, the loop crossover frequency, f c , should be selected as the frequency at which the phase 0.8v r filt c filt 3111 f09 fb ltc3111 comp + ? figure 9. internal loop filter loop compensation example this section provides an example illustrating the design of a compensation network for a typical ltc3111 application circuit. in this example a 5 v regulated output voltage is generated with the ability to supply a 500 ma load from an input power source ranging from 3.5 v to 15v. to reduce switching losses a 800 khz switching frequency has been chosen for this example. in this application the maximum inductor current ripple will occur at the highest input volt - age. an inductor value of 4.7 h has been chosen to limit ltc 3111 3111fa for more information www.linear.com/ltc3111
23 figure 10. converter bode plot v in = 3.5v, v out = 5v, r = 10 (hz) ?20 (db) (deg) ?10 10 30 40 10 1k 10k 1m 3111 f10 ?30 100 100k 20 0 ?90 ?40 ?180 ?135 ?45 gain phase 45 90 ?255 0 ?270 f c = 40khz applications information of the buck-boost converter reaches C180. as a result, at the loop crossover frequency the total phase will be simply the 60 of phase provided by the error amplifier as shown: phase margin = ? buck-boost + ? erroramplifier + 180 = C180 + 60 + 180 = 60 similarly, if a phase margin of 45 is required, the target crossover frequency should be picked as the frequency at which the buck-boost converter phase reaches C195 so that the combined phase at the crossover frequency yields the desired 45 of phase margin. this example will be designed for a 60 phase margin to ensure adequate performance over parametric variations and varying operating conditions. as a result, the target crossover frequency, f c , will be the point at which the phase of the buck-boost converter reaches C180. it is generally difficult to determine this frequency analytically given that it is significantly impacted by the q factor of the resonance in the power stage. as a result, it is best determined from a bode plot of the buck-boost converter as shown in figure 10. this bode plot is for the ltc3111 buck- boost converter using the previously specified power stage parameters and was generated from the small-signal model equations using ltspice ? software. in this case, the phase reaches C180 at 40 khz making f c = 40 khz the target crossover frequency for the compensated loop. from the bode plot of figure 10 the gain of the power stage at the target crossover frequency is 13.5 db. therefore, in order to make this frequency the crossover frequency in the compensated loop, the total loop gain at f c must be adjusted to 0db. to achieve this, the gain of the compen- sation network must be designed to be C13.5 db at the crossover frequency. at this point in the design process, there are three con - straints that have been established for the compensation network. it must have C13.5 db of gain at f c = 40 khz, a peak phase boost of 60 that is centered at f c = 40 khz. one way to design a compensation network to meet these targets is to simulate the compensation error amplifier bode plot in ltspice for the typical compensation network shown on the front page of this data sheet. then, the gain, pole and zero frequencies can be iteratively adjusted until the required constraints are met. alternatively, an analytical approach can be used to design a compensation network with the desired phase boost, center frequency and gain. in general, this procedure can be cumbersome due to the large number of degrees of freedom in the t ype iii com- pensation network . however the design process can be simplified by assuming that both the compensation zeros occur at the same frequency, f z , and both higher order poles (f pole2 and f pole3 ) occur at the common frequency, f p . in most cases this is a reasonable assumption since the zeros are typically located between 1 khz and 10khz and the poles are typically located near each other at much higher frequencies. given this assumption, the maximum phase boost, provided by the compensation error amplifier is determined simply by the amount of separation between the poles and zeros as shown by the following equation: max = 4 ? arctan f p f z ? ? ? ? ? ? C 270 ltc 3111 3111fa for more information www.linear.com/ltc3111
24 applications information a reasonable choice is to pick the frequency of the poles, f p , to be 50 times higher than the frequency of the zeros, f z , which provides a peak phase boost of approximately 60 as was assumed previously. next, the phase boost must be centered so that the peak phase occurs at the target crossover frequency. the frequency of the maximum phase boost, f center , is the geometric mean of the pole and zero frequency as: f center = f p ? f z = 50 ? f z ? 7 ? f z therefore, in order to center the phase boost given a factor of 50 separation between the pole and zero frequencies, the zero should be located at one-seventh of the crossover frequency and the poles should be located at seventh times the crossover frequency as given by the following equation: f z = f c 7 = 40khz 7 = 5.71khz f p = 7 ? f c = 7 ? 40khz = 280khz this placement of the poles and zeros will yield a peak phase boost of 60 that is centered at the crossover frequency, f c . next, in order to produce the desired target crossover frequency, the gain of the compensation network at the point of maximum phase boost, g center , must be set to C13.5db. the gain of the compensated error amplifier at the point of the phase gain is given by: g center = 10 ?log 2 ? ? f p 2 ? ? f z ( ) 3 ? r1?c fb ( ) 2 ? ? ? ? ? ? ? ? db assuming a multiple of 50 separation between the pole and zero frequencies this can be simplified to the follow- ing expression: g center = 20 ?log 50 2 ? ? f c ?r1?c fb ? ? ? ? ? ? db this equation completes the set of constraints needed to determine the compensation component values. specifi- cally, the two zeros, f zero1 and f zero2 , should be located near 5.71 khz. the two poles, f pole2 and f pole3 , should be located near 280 khz and the gain should be set to provide a gain at the crossover frequency of g center = C13.5db. the first step in defining the compensation component values is to pick a value for r1 that provides an acceptably low quiescent current through the resistor divider. a value of r 1 = 1 m is a reasonable choice. next, the value of c fb can be found in order to set the error amplifier gain at the crossover frequency to C13.5db as follows: g center = C13.5db = 20 ?log 50 2 ? ? 40khz ?1m ? ?c fb ? ? ? ? ? ? c fb = 50 2 ? ? 40khz ?1m ? ?10 C 13.5 20 ? 1000pf the compensation poles can be set at 280 khz and the zeros at 5.71 khz by using the expressions for the pole and zero frequencies given in the previous sections. setting the frequency of the first zero, f zero1 , to 5.71 khz results in the following value for r fb : r fb = 1 2 ? ? 5.71khz?1000pf ? 28.0k ? this leaves the free parameter, c pole , to set frequency f pole1 to the common pole frequency of 280 khz as given: c pole = 1 2 ? ? 280khz ? 28k ? ? 22pf ltc 3111 3111fa for more information www.linear.com/ltc3111
25 figure 11: compensation error amplifier bode plot figure 12: complete loop bode plot (hz) ?20 (db) (deg) ?10 10 30 40 10 1k 10k 1m 3111 f11 ?30 100 100k 20 0 0 ?40 ?45 90 45 ?90 40khz, 57 40khz, ?14db gain phase (hz) 10 0 ?90 (db) (deg) 10 20 30 40 100 1k 10k 100k 1m 3111 f12 ?10 ?20 ?30 ?40 50 60 ?45 0 45 90 ?135 ?180 ?225 ?270 135 180 40khz, 59 gain phase applications information next, c ff can be chosen to set the second zero, f zero2 , to the common zero frequency of 5.71khz. c ff = 1 2 ? ? 5.71khz ?1m ? ? 27pf finally, the resistor value r ff can be chosen to place the second pole at 280khz. r ff = 1 2 ? ? 280khz ? 27pf ? 20k ? now that the pole frequencies, zero frequencies and gain of the compensation network have been established, the next step is to generate a bode plot for the compensated error amplifier to confirm its gain and phase properties. a bode plot of the error amplifier with the designed com - pensation component values is shown in figure 11. the bode plot confirms that the peak phase occurs at 40 khz and the phase boost at that point is 57. in addition, the gain at the peak phase frequency is C14 db which is close to the design target. the final step in the design process is to compute the bode plot for the entire designed compensation network and confirm its phase margin and crossover frequency. the complete loop bode plot for this example is shown in figure 12. the loop crossover frequency is 40 khz and the phase margin is approximately 59. the bode plot for the complete loop should be checked over all operating conditions and for variations in component values to ensure that sufficient phase margin exist in all cases. the stability of the loop should also be confirmed via time domain simulation and by the transient response of the converter in the actual circuit . ltc 3111 3111fa for more information www.linear.com/ltc3111
26 typical applications 1, 2, 3 li-ion to 5v wide v in to 5v out efficiency sw1 0.1f 27pf 1f 33pf 1m 191k 154k r 3111 ta02a 20k 680pf 26.1k 0.1f v in 3v to 12.6v 4.7h sw2 bst1 bst2 v in ltc3111 pgnd v out 22f v out 5v 750ma v in > 4v 10f 1 to 3-cell li-ion pwm/sync burst pwm run fb v cc snsgnd sgnd comp + number of cells 1 2 3 r 274k 698k 1.13m load current (a) 50 efficiency (%) 70 90 100 0.0001 0.001 0.1 1 10 3111 ta02b 30 0.01 80 60 40 v in = 3.6v v in = 7.2v v in = 10.8v ltc 3111 3111fa for more information www.linear.com/ltc3111
27 typical applications ltc3111 synchronized to a 1.5mhz clock, 5v/1a output 3.3v backup from a high voltage capacitor bank runs down to v in = 2v with 500ma load sw1 0.1f 15pf mbr0520l optional 1m 191k 3111 ta03a 270pf 57.6k 0.1f v in 2.5v to 15v 2.2h sw2 bst1 bst2 v in ltc3111 sgnd pgnd v out 1.5mhz clock 22f 1f v out 5v 1a v in > 5v 10f pwm/sync run fb v cc snsgnd comp off on sw1 0.1f 33pf 36pf mbr0520l optional 1m 316k 3111 ta04a 20k 1600pf 24.3k 0.1f v in 2v to 15v 4.7h sw2 bst1 bst2 v in ltc3111 v out v cc 33f 1f v out 3.3v 500ma 100f c in 214mf pwm/sync run fb v cc v cc snsgnd comp sgnd pgnd v in 5v/div v out 2v/div i out 500ma/div 2 sec/div 3111 ta04b power supply removed pwm/sync 5v/div sw1 10v/div inductor current 1a/div sw2 5v/div 500ns/div 3111 ta03b ltc 3111 3111fa for more information www.linear.com/ltc3111
28 typical applications stepped response from 1 or 2 li-ion to 12v adapter source v out = 5v sw1 0.1f 27pf 1f 33pf 1m 191k 3111 ta05a 20k 680pf 26.1k 0.1f 12v adapter 4.7h sw2 bst1 bst2 v in ltc3111 v out v cc 1- or 2-series li-ion cells 22f v out 5v 1.5a v in > 5v 47f pwm/sync run fb snsgnd comp off on b520c burst pwm lt ? 4352 ideal diode sgnd pgnd v in 2v/div two li-ion cells v out 500mv/div inductor current 1a/div 1ms/div i out = 500ma 3111 ta05b custom input undervoltage lockout thresholds sw1 0.1f 27pf 1f 33pf 1m 191k 316k 1m 3111 ta08a 20k 680pf 26.1k 0.1f v in 5v to 15v enabled when v in reached 5v disabled when v in falls below 4.5v 4.7h sw2 bst1 bst2 v in ltc3111 v out v cc v cc v cc 22f v out 5v 1.5a 10f pwm/sync run fb snsgnd comp sgnd pgnd v in 10v/div v out 5v/div inductor current 1a/div 2ms/div r load = 3.3 3111 ta08b v in 10v/div v out 5v/div inductor current 1a/div 2ms/div r load = 3.3 3111 ta08c ltc 3111 3111fa for more information www.linear.com/ltc3111
29 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) ltc 3111 3111fa for more information www.linear.com/ltc3111
30 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (mse16) 0213 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev f) ltc 3111 3111fa for more information www.linear.com/ltc3111
31 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 1/14 clarified graphs 1, 4, 5, 6 ltc 3111 3111fa for more information www.linear.com/ltc3111
32 ? linear technology corporation 2013 lt 0114 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3111 related parts typical application part number description comments ltc3533 2a (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 40a, i sd < 1a, dfn package ltc3113 3a (i out ), 2mhz low noise buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.5v, i q = 40a, i sd < 1a, dfn and tssop packages ltc3534 7v, 500ma (i out ), synchronous buck-boost dc/dc converter v in : 2.4v to 7v, v out : 1.8v to 7v, i q = 25a, i sd < 1a, dfn and gn packages ltc3129/ ltc3129-1 15v , 200ma (i out ), synchronous buck-boost dc/dc converter with 1.3a quiescent current v in : 2.42v to 15v, v out : 1.4v to 15.75v, i q = 1.3a, i sd < 100na, qfn and msop packages ltc3112 15v, 2.5a (i out ), synchronous buck-boost dc/dc converter v in : 2.7v to 15v, v out = 5v, i q = 50a, i sd < 1a, dfn and tssop packages ltc3785 10v, high efficiency, synchronous, no r sense ? buck-boost controller v in : 2.7v to 10v, v out : 2.7v to 10v, i q = 86a, i sd < 15a, qfn package ltc3115-1/ ltc3115-2 40v, 2a (i out ), synchronous buck-boost dc/dc converter v in : 2.7v to 40v, v out = 2.7v to 40v, i q = 30a, i sd < 1a, dfn and tssop packages ltc3789 high efficiency, synchronous, 4-switch buck-boost converter v in : 4v to 38v, v out : 0.8v to 38v, i q = 3ma, i sd < 60a, qfn and ssop packages ltc3122 15v, 2.5a (i out ), synchronous step-up dc/dc converter with output disconnect v in :1.8v to 5.5v, v out : 2.2v to 15v. i q = 25a, i sd < 1a, dfn and msop packages regulated 12v output from wide range input supply wide v in to 12v out efficiency sw1 0.1f 39pf 1f 18pf 2.21m 158k 3111 ta06a 20k 1000pf 44.2k 0.1f v in 2.5v to 15v 10h sw2 bst1 bst2 v in ltc3111 v out v cc v cc 22f v out 12v 0.5a, v in > 5v 1.0a, v in > 9v 10f pwm/sync burst pwm run fb snsgnd comp off on sgnd pgnd load current (a) 0.0001 70 efficiency (%) 80 90 100 0.001 0.01 0.1 1 10 3111 ta06b 60 50 40 30 v in = 5v v in = 12v burst pwm ltc 3111 3111fa for more information www.linear.com/ltc3111

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